Telelogic® Statemate®

Telelogic Statemate is a graphical design, simulation and prototyping tool for the rapid development of complex embedded systems. It enables engineers to graphically capture their system requirements, specifications, and designs using a combination of the Unified Modeling Language and traditional functional design notations. The graphical models captured in Telelogic Statemate are simulated on the host computer allowing errors in the requirements and specifications to be discovered early in the process when they are inexpensive to fix. Telelogic Statemate automatically generates documentation, prototype code, and test vectors, and enables corporate re-use of key systems components. Built on an open API that enables seamless integration with leading requirements traceability and configuration management tools, Telelogic Statemate has emerged as the standard for complex embedded system

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