Telelogic® Statemate® Highlights

Telelogic Statemate extends UML systems designs and simulation benefits to users. The Telelogic Statemate Design Entry allows the systems engineer to create a graphical model of the system being designed, based on standard engineering diagrams including some UML diagrams:

• Data and Control Flow Diagrams
• Structure Diagrams
• Truth Tables
• Flowcharts
• Control Law Block Diagrams
• UML diagrams include use Case Diagrams, Sequence Diagrams and Statecharts

These diagrams, plus input via a menu-driven user interface, enables engineers tasked with implementing and testing the system to effectively detail the communication of the specification.

A Telelogic Statemate model is a formal model that can be simulated and automatically translated into code. Telelogic Statemate's visualization capabilities vastly improve team communication among design teams at the OEM and supplier. The product's simulation capabilities allow system engineers to test the specification to ensure correctness.

Some benefits of Telelogic Statemate's Simulator include:

• Highlights Active States, Functions, and Scenarios during simulation
• Mockup panels provide both input to and output from the simulation
• Simulates an incomplete design, allowing the user to build the model and simulate it in an iterative top-down, bottom-up, or middle-out fashion
• The simulator environment provides all the traditional debugging apparatus such as waveforms, monitors, and debugger windows. This allows you to analyze the specification in order to ensure that its behavior is correct and to capture the test data

For more information on Telelogic Statemate, please click here.